(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to improve the density and performance of a metal oxide semiconductor field effect transistor, (MOSFET), device, via use of enhanced processes and non-conventional gate materials.
(2) Description of Prior Art
The advent of micro-miniaturization, or use of sub-micron features, for the fabrication of MOSFET devices, is dependent on the ability of the semiconductor industry to develop new processes, and new materials, to allow the fabrication of sub-micron MOSFET devices to be realized. The attainment of sub-micron features, of 1000 Angstroms or less, realized via advancements in several semiconductor fabrication disciplines, such as photolithography, and reactive ion etching, (RIE), are benefitted by the use of dielectric layers exhibiting higher dielectric constants than the conventionally used silicon dioxide, as well as benefitted by the use of metal gate structures, with lower resistance than the conventionally used polysilicon gate structure. The need for thinner layers and structures, for use in sub-micron MOSFET devices, make the use of the high k gate insulator layer, and the metal gate structure imperative. However the high k insulator layers can not withstand temperatures greater than about 500.degree. C. Specific process sequences, conventionally performed after gate insulator formation can degrade the integrity of the high k gate insulator layer.
This invention will describe a process sequence that allows the narrow, and shallow dopant profiles of anti-punchthrough, and of source/drain regions, to be obtained, and then retained via self-aligned processes, performed prior to the formation of the high k gate insulator layer. In addition the spacer sidewall procedure, is performed prior to the formation of the narrow anti-punchthrough region, thus preserving the desired narrow profile of this region. This is accomplished via use of a dummy gate structure, used to provide a structure for accommodation of the sidewall spacers. After formation of the source/drain region, and removal of the dummy gate structure, the anti-punchthrough region is formed in the region of the semiconductor substrate which previously was occupied by the dummy gate structure. A high k gate insulator layer is then formed on the surface vacated by the dummy gate structure, followed by the formation of a metal gate structure, overlying the high k gate insulator layer, in the space vacated by the dummy gate structure, butting against the previously formed spacer sidewalls. Prior art, such as Lee et al, in U.S. Pat. No. 5.656,225, as well as Kao et al, in U.S. Pat. No. 5,688,700, describe processes for enhancing MOSFET devices, in terms of narrow and shallow dopant regions, as well as the use of dummy gate structures, however none of these prior arts describe the use of a high k gate insulator layer, and an overlying metal gate structure, formed after the self-aligned creation of narrow, and shallow dopant regions.